IEEE Conference on Secure RISC-V (SECRISC-V) Architecture Design Exploration and Software Applications
The SECRISC-V conference is specifically focused on presenting the latest advancements in secure RISC-V architecture and software applications. Its scope includes discussions on secure cores, ISA extensions, hardware-software co-design, and forthcoming RISC-V security solutions for IoT, HPC, and cloud computing. Additionally, the conference emphasizes secure software development and the significance of open-source software in secure RISC-V systems. SECRISC-V primary goal is to enhance understanding and foster collaboration in developing secure and efficient RISC-V systems.

• Submission: October 15th, 2024
• Notification: October 22nd, 2024
• Final Version: November 1st, 2024
• Conference Dates: Thursday/Friday November 14th and 15th, 2024

• Final Location: TBD (We will be in Beautiful Novi Sad, Serbia!)

Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:

• Secure cores and multicores
• ISA extensions for Security
• Software and hardware obfuscation Techniques
• Secure, efficient, and lightweight hardware implementations
• Hardware security solutions for machine learning
• Secure design for emerging applications: IoT, robotics, wearable computing, etc.
• Architectural designs and hardware security solutions for HPC, Data Centers and cloud computing
• Hardware virtualization and isolation for security
• Hardware-Software co-design solutions for graph analytics
• Post-quantum cryptosystem designs
• Software and core authentication
• Secure execution environment
• Secure root of trust bios
• Memory subsystem organization to secure data accesses
• Network-on-Chip (NoC) security feature to process and compute isolation.
• Secure Software Development for RISC-V Platforms
• Secure Compiler and Toolchain Development for RISC-V
• Security-Oriented Operating Systems for RISC-V
• Software-Based Cryptographic Implementations and Optimization
• RISC-V Software Testing and Verification Tools
• Embedded Software Security for IoT and Edge Devices
• Secure Middleware for Distributed RISC-V Systems
• End-to-End Software Security in RISC-V Ecosystems

• All papers must be written in English and should describe original work. The length of the paper is limited to a maximum of 6 pages (in the standard IEEE conference double column format). Only full papers are accepted for submission. Papers will be refereed through a blind process for technical merit and content.
• Student Poster Submission: Title and abstract - must be submitted in PDF format.

Program Committee