International Workshop on Secure RISC-V (SECRISC-V) Architecture Design Exploration
seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).

Keynote Speakers

RISC-V Support for Secure Context-Aware Computing

branko Brief Bio: Dr. Milosavljević received his Ph.D. degree from the University of Novi Sad, in 2003. He is currently a Professor of computer science with the Faculty of Technical Sciences, University of Novi Sad. He has published over 150 articles and participated or lead in more than 20 projects. His research interests include digital libraries, net-centric software architectures, and context-aware computing.

Domain Specific Language (DSL) Support for Secure RISC-V Execution

goran Brief Bio: Dr. Goran Sladić received his B.Sc., M.Sc., and Ph.D. degrees in computer science from the Faculty of Technical Sciences, University of Novi Sad, in 2002, 2006, and 2011, respectively. He is currently a Professor of computer science with the Faculty of Technical Sciences, University of Novi Sad. He has published over 70 articles and participated in more than 20 projects. His research interests include cyber security, blockchain, software architectures, and context-aware computing.

Topics

Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:

Secure cores and multicores
ISA extensions for Security
Software and hardware obfuscation Techniques
Secure, efficient, and lightweight hardware implementations
Hardware security solutions for machine learning
Secure design for emerging applications: IoT, robotics, wearable computing, etc.
Architectural designs and hardware security solutions for HPC, Data Centers and cloud computing
Hardware virtualization and isolation for security
Hardware-Software co-design solutions for graph analytics
Post-quantum cryptosystem designs
Software and core authentication
Secure execution environment
Secure root of trust bios
Memory subsystem organization to secure data accesses
Network-on-Chip (NoC) security feature to process and compute isolation.

Submission Formats

We are adding a poster session to this year's workshop for greater active student participation.

Oral Presentation Submission: The paper must be submitted in PDF format. The content of the submission is limited to four (4) pages - 8.5"x11" in standard IEEE two-column format (both blind and non-blind submission forms are permitted).
Poster Submission: Title and abstract - must be submitted in PDF format.

Program Committee

Michel A. Kinsy

Workshop Chair & Organizer
Secure, Trusted, and Assured Microelectronics (STAM) Center
Arizona State University

Lake Bu

Charles Stark Draper Laboratory

Kurt L. Keville

Massachusetts Institute of Technology (MIT)

Xinfei Guo

Michigan University - Shanghai Jiao Tong University

Alan Ehret

Secure, Trusted, and Assured Microelectronics
(STAM) Center, Arizona State University

Jasmine A. Jones

Harvard University

Workshop on Secure RISC-V Architecture Design

In-Person in Tempe, Arizona

Important Dates & Deadlines

Location