Important Update: Due to the continuing impact of the COVID-19 pandemic, the 2021 IEEE International Symposium on Workload Characterization and SECRISC-V 2021 workshop will be virtual events (November 7 - November 9, 2021).

Second International Workshop on Secure RISC-V (SECRISC-V) Architecture Design Exploration
seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).

Important Dates & Deadlines

Keynote Speakers

To be announced soon!


Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:

The paper must be submitted in PDF format. The content of the submission is limited to four (4) pages - 8.5"x11" in standard IEEE two-column format (both blind and non-blind submission forms are accepted).

Program Committee


Michel A. Kinsy

Workshop Chair & Organizer
Secure, Trusted, and Assured Microelectronics (STAM) Center
Arizona State University

Lake Bu

Charles Stark Draper Laboratory

Kurt L. Keville

Massachusetts Institute of Technology (MIT)

Mihailo Isakov

Secure, Trusted, and Assured Microelectronics
(STAM) Center, Arizona State University

Xinfei Guo

Michigan University - Shanghai Jiao Tong University

Alan Ehret

Secure, Trusted, and Assured Microelectronics
(STAM) Center, Arizona State University

Jasmine A. Jones

Harvard University

More coming!