Second International Workshop on Secure RISC-V
(SECRISC-V) Architecture Design Exploration
seeks original research papers on the design,
implementation, verification, and evaluation of
micro-architecture security features, hardware-assisted
security techniques, and secure executions around the RISC-V
instruction set architecture (ISA).
Abstract: An exploration of a few problems, a brief history lesson, and a glimpse at research that is rethinking architecture for the future.
Brief Bio: Dr. Rudd is a Computer Systems Researcher at the Laboratory for Physical Sciences and formerly led the Computer Architecture and Computer Engineering team. He is working on enterprise-class computer architecture enhancements extending commodity architectures (like Arm and RISC-V) to support large address spaces providing scalability, abstraction, and safety &s; security. He has also performed research in the areas of advanced computer architecture, emerging memory technology, and rapid development and deployment. He is the sole or first inventor on four hardware–software co-design patents. Dr. Rudd has worked in government, industry, academia, and the military and received his Ph.D., M.S., and B.S. in Electrical Engineering from Stanford University.
Abstract: Zero Trust (Trust no one, but always verify) has been a hot topic in the network security world, where it shifts the paradigm from trust-based on physical connectivity to the one that involves always authenticating every access. In this talk, we shall discuss a holistic view of Zero Trust principles right from the RISC-V silicon up to software-level, and how we can improve the trust of the platform and every component in it. In the context of RISC-V based systems, we will cover related topics including (i) platform-level Trusted Execution Environment (TEE) design with configurable and dynamic Trusted Computing Base (TCB), (ii) distributed Root-of-Trust (RoT) to facilitate mutual authentication, encryption of data exchanged between every component on platform/ SoC, and platform-wide remote attestation to verify the firmware integrity of every component in the platform, and (iii) supply chain security using logic locking to mitigate trojans, counterfeits, etc.
Brief Bio: Suresh Sugumar is an Executive Director at Technology Innovation Institute (TII) which is a premier research agency based in Abu Dhabi, UAE. His research focuses on Zero Trust Security for SoCs, and the responsibilities involve leading a team to build an open-source SoC, advancing security research and IP development. He actively contributes to RISC-V.org working groups for confidential computing, trusted execution environment, control-flow integrity, and side-channel resistant microarchitecture. Suresh is a Senior Member of IEEE, holds 15+ patents, and published several articles and research papers in various international conferences. Before joining TII in 2021, Suresh worked at Intel, Qualcomm, and Mediatek for 18+ years. He earned his MBA from INSEAD, and an MS from the Birla Institute of Technology & Science, Pilani.
Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:
The paper must be submitted in PDF format. The content of the submission is limited to four (4) pages - 8.5"x11" in standard IEEE two-column format (both blind and non-blind submission forms are accepted).