Second International Workshop on Secure RISC-V
(SECRISC-V) Architecture Design Exploration
seeks original research papers on the design,
implementation, verification, and evaluation of
micro-architecture security features, hardware-assisted
security techniques, and secure executions around the RISC-V
instruction set architecture (ISA).
10:00–10:10 |
Welcome note by Dr. Michel A. Kinsy |
10:10–10:55 |
Rethinking Architecture—Safety & Security (and More)
|
|
11:00–11:30
|
Hardware-Assisted Control Flow Integrity Schemes on RISC-V
|
|
11:30–12:00
|
A Secure Architecture for Return Address Corruption
|
12:00–12:30 |
Lunch break
|
12:35–1:20 |
RISC-V Zero Trust Platform Security Model
|
|
1:20–1:50
|
Commoditizing Secure Enclave based Computing in RISC-V Multicore Architectures
|
|
1:50–2:20
|
Isadora: Automated Information Flow Property Generation for Hardware Designs
|
2:20–2:30 |
Break
|
|
2:30–3:00
|
A RISC-V Simulator for Performance, Energy, and Information Leakage Modeling of Large Multicore Processors
|
3:00–3:30 |
RISC-V Based Lightweight Attack Resilient Small Embedded SoC Design
|
|
3:30–3:55
|
Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities
|
3:55–4:00+ |
Closing remarks and feedback from attendees |
|
4:00+–4:25+
|
Hardware-Assisted Return-Oriented Programming Mitigation for RISC-V
|
Camera-ready version and presentation resources - [Latex Template] and [PowerPoint Template].
Please note that the paper must be submitted in PDF format. The content of the submission is limited to four (4) pages.